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نویسندگان مقالات پربازدید :
مجله مواد الکترونیکی 2013
جزئیات رویداد
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همایش ، رویداد ، ژورنال

  • failure analysis of board-level sn-ag-cu solder interconnections under jedec standard drop test

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    • تاریخ ارائه: 1392/07/24
    • تاریخ انتشار در تی پی بین: 1392/07/24
    • تعداد بازدید: 902
    • تعداد پرسش و پاسخ ها: 0
    • شماره تماس دبیرخانه رویداد: -
     this work investigates the board-level drop reliability of printed circuit boards (pcbs) assembled using three chip-size packages subjected to joint electron device engineering council (jedec) standard drop test condition b. the acceleration and dynamic strain responses at several locations of the board-level package in the time and frequency domain are comprehensively investigated. the results in the time domain suggest that the dynamic response of the board-level package has two phases: forced vibration and free vibration. the maximum response occurs at the first half free vibration cycle. the acceleration response at the center of the pcb is larger than at the edges, whereas the dynamic strain response is just the opposite. the results in the frequency domain show that the first mode is fundamental. in addition, failure analysis is performed using the dye-and-pry test and cross-section test, suggesting that the brittle cracking occurs at the layer between the integrated circuit (ic) pad and the solder, not only through intermetallic compound (imc) but also along the surface between the ic pad and imc.

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